Register for New Verification Workshop Covering AMBA, DDR, MIPI, and PCIe I/Fs

Author: 911EDA News Desk
Aug 17, 2016





Attend Cadence's complimentary two-day workshop to learn how you can do a more thorough job of verifying your SoC designs. Cadence experts will guide you through new protocol developments and demonstrate the application of Verification IP (VIP) to debug these interfaces: PCI Express® (PCIe®) Gen4, ARM® AMBA® AHB5, MIPI® CSI-2/DSI-2/C-PHY, and DDR4. You’ll gain a new understanding of these interfaces and see how Cadence® VIP simplifies the debugging process.

Each topic will be covered by a lecture led by a verification expert. Lunch will be provided.

Seating is limited. Reserve your space today! 

Date, Time, and Location
September 20 – 21, 2016
9:30am – 4:30pm
Cadence Headquarters, Building 6 Lobby
2655 Seely Avenue, San Jose, CA 95134



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