Mentor Paper: DDR4 Board Design and Signal Integrity Verification Challenges

Author: 911EDA News Desk
May 22, 2017

This Mentor white paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers.

This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching Noise characterization.

To download this paper, click here.

AltiumMentor GraphicsCadenceOrCAD